DARPA Grant Empowers University of Texas at Dallas to Develop Tools for Designing Nanoscale Computer Chips
The tiniest transistors on integrated circuits now measure just a few nanometers wide — 33,000 times smaller than the thickness of a sheet of paper. At that size, however, the components can behave in unexpected ways due to quantum physics.
The emergence of chips with transistors at that scale has created a need for computer modeling tools that can simulate and predict the material performance of devices so small they defy traditional design rules. Currently, only supercomputers can calculate material properties such as size, shape and density of device structures in the nanometer range, and a single simulation can take days or weeks.
A team of five University of Texas at Dallas researchers is working to develop computational modeling tools that use artificial intelligence to do the work 1,000 times faster than simulations processed by supercomputers. The Erik Jonsson School of Engineering and Computer Science researchers received a $1 million grant from the Defense Advanced Research Projects Agency (DARPA) to demonstrate the proof-of-concept materials design approach to predicting material properties at the nanometer scale.
The AI-based tools will aid in the design of smaller, faster devices — specifically the development of high-performance terahertz (THz) devices for DARPA applications — and could have broader impacts on advanced materials, including next-generation battery technology.
Current transistor design tools rely on macroscopic material properties, which are not accurate for devices built at nanometer scales, where quantum physics takes precedence.
“The project is based on the question: How can we accelerate the materials design cycle 1,000 times faster and maintain a very high level of accuracy?”
Dr. Kyeongjae (KJ) Cho, professor of materials science and engineering in the Erik Jonsson School of Engineering and Computer Science
“Commercial mainstream technology is getting small enough that it’s overlapping with the quantum domain, and that’s causing a lot of manufacturing and design challenges,” said Dr. Kyeongjae (KJ) Cho, principal investigator on the grant and professor of materials science and engineering. “The project is based on the question: How can we accelerate the materials design cycle 1,000 times faster and maintain a very high level of accuracy?”
The shrinking of semiconductor technology has resulted in chips that can hold billions of transistors, making it possible to manufacture smaller, faster and more powerful electronic devices that use less power.
“Scaling down is a major reason why we’ve gone from a computer that took up a whole room to something we carry around in our pockets that has remarkably more computing power and capability than the original computers had,” said Dr. Chadwin Young, associate professor of materials science and engineering. “We’re getting to the point now where materials in a computer chip may be just several atoms thick, and that’s when it begins to potentially creep into some of these quantum effects.”
A smaller transistor means the placement of each atom becomes much more critical to the performance of the device, said Dr. Cormac Toher, assistant professor of materials science and engineering.
“The idea behind our project is to be able to speed up simulations, so instead of taking months to model one configuration, we could try lots of different configurations at the same time,” Toher said.
The tool will allow researchers to test individual transistor designs and pinpoint issues early in the process before they are incorporated into larger semiconductor circuitry, Young said.
“Based on theoretical aspects of a material, we can have an idea of how it will impact semiconductor device operation,” Young said. “Every now and again we may run into something unexpected, and these simulations will help us understand why that occurs.”
Other UT Dallas researchers working on the project include Dr. Massimo V. Fischetti, professor of materials science and engineering and a TI Distinguished Chair in Nanoelectronics; and Dr. Kenneth O, professor of electrical engineering, director of the Texas Analog Center of Excellence and the Texas Instruments Distinguished University Chair.