IIT Delhi Researcher in Collaboration with NUS Designs Device for High Density Magnetic Memory

New Delhi: As we are moving toward a data-driven age, there is a need for faster and very low power computing. Memories play a crucial role in this, as for faster processing of data, the CPU rapidly reads and writes on the memory.

The main memory, i.e., the Random-access memories (RAMs), are most commonly used in modern computer architecture. These are SRAMs and DRAMs, which are based on CMOS technology. They are fast but volatile, which means they require a constant supply of power, this consumes lots of energy. But if these could be made non-volatile, then computing could be made more energy efficient.

Spintronics memories like spin-transfer torque magnetoresistive RAM (STT-MRAM) and spin-orbit torque magnetoresistive RAM (SOT-MRAM) are inherently non-volatile. They consume no power at standby. Also, their operation speeds are comparable to RAMs. Hence, these spintronics memories are the most potential candidates for replacing current electronic RAMs.

Figure 1 Spintronics memories

SOT-MRAMs are better than STT-MRAM in terms of reliability and writing speed but lags behind in achieving high integration density. This is because, unlike STT-MRAM, which is a two-terminal device and needs one transistor for reading and writing operation, the SOT-MRAMs requires two transistors each for reading and writing. Thus SOT-MRAM requires a larger area per bit as compared to STT-MRAM, as shown in figure 1.

Also, SOT-MRAM is less prone to breakdown due to separate read and write paths, this is absent in STT-MRAMs. Hence, SOT-MRAM is the preferred choice among the research community however significant work is required to increase their areal density.

In a collaborative work between Prof. Rahul Mishra from the Centre for Applied Research in Electronics (CARE), IIT Delhi and Prof. Hyunsoo Yang from the National University of Singapore (NUS) a possible solution for achieving higher integration density in SOT-MRAMs was proposed and experimentally demonstrated.

 

Prof. Rahul Mishra, CARE, IIT Delhi said, “We demonstrated a shared write channel based multibit SOT cell scheme, which reduces the number of transistors required per bit. This cell design requires half the area compared to conventional SOT MRAM, thus almost doubles the area efficiency of the memory chip”.

 

The below figure represents the basic idea and schematic of a shared channel SOT-MRAM.

Figure 2– Shared channel scheme for increasing the area efficiency

To make the above design feasible, the team designed a magnetic memory device, which can be programmed by application of gate voltage. The gate voltage was used to migrate oxygen ions in the device, which resulted in modulation of the spin current polarity as shown in the Figure 3. Thus, cells can now be written individually, and hence they obtained a full-fledged, working area-efficient SOT memory. The work was published in Physical Review applied (https://journals.aps.org/prapplied/abstract/10.1103/PhysRevApplied.15.024063)

 

Prof. Mishra further said, “The results of this work could eventually help to develop low power electronic devices. The frequent charging of wireless electronic devices such as mobile phone, IoT devices, etc would be significantly reduced with the proposed device. It would be especially useful for industrial applications where sensors are put in locations, which are not easy to access. Low power and high-density memory devices would not only be helpful in reducing global energy footprint, but the saved energy can also be used for extra computational tasks”.

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